Graphene Oxide/Polystyrene Bilayer Gate Dielectrics for Low-Voltage Organic Field-Effect Transistors

Here, we report on the use of a graphene oxide (GO)/polystyrene (PS) bilayer as a gate dielectric for low-voltage organic field-effect transistors (OFETs). The hydrophilic functional groups of GO cause surface trapping and high gate leakage, which can be overcome by introducing a layer of PS—a hydrophobic polymer—onto the top surface of GO. The GO/PS gate dielectric shows reduced surface roughness and gate leakage while maintaining a high capacitance of 37.8 nF cm−2. The resulting OFETs show high-performance operation with a high mobility of 1.05 cm2 V−1 s−1 within a low operating voltage of −5 V.


Introduction
Organic field-effect transistors (OFETs) have attracted great attention because of their potential applications in flexible and bendable displays with high field-effect mobility, low-temperature processability, and flexibility [1,2]. Although high-performance OFETs have been consistently reported in the past decade, most of the studies have focused on devices employing rigid inorganic dielectrics, such as silicon dioxide (SiO 2 ) and aluminum oxide [3][4][5]. Therefore, polymer dielectrics, such as poly(methyl methacrylate), poly(vinyl alcohol), polyimide, and poly (4-vinylphenol), have been extensively studied as alternatives to inorganic dielectric layers in OFETs because the former offer the advantages of solution processes and the need for flexible device applications [6][7][8][9]. However, single layers of such polymer dielectrics have some limitations with regard to working in low-voltage driving OFETs. Realization of low-voltage OFETs necessitates the use of high-capacitance (C i ) gate dielectrics. In general, C i can be expressed as C i = k·ε 0 ·d −1 , where k is the dielectric constant, ε 0 is the permittivity of the dielectric material, and d is the dielectric thickness. From this equation, it is clear that the use of a high-k gate dielectric film or a reduction of the thickness of the dielectric layer is necessary for increasing C i . With only a few exceptions, polymer dielectrics generally have low k; thus, the thickness of the polymer layer must be reduced to a scale of at least a few nanometers to increase C i . However, the insulating properties of polymer dielectrics degrade severely with a reduction in film thickness [10]. Therefore, it is highly challenging to develop novel gate dielectric materials that simultaneously are thin and exhibit good dielectric properties with high k for application to low-voltage OFETs.
On account of its outstanding electrical, mechanical, and chemical properties, graphene has been intensively studied for application as a semiconductor, electrode, and encapsulation layer in OFETs [4,[11][12][13][14]. In particular, graphene derived from graphene oxide (GO), which is referred to as reduced GO (rGO), has attracted much attention for application to flexible devices because of its thinness, excellent electrical properties, and mechanical flexibility [15][16][17]. Most researchers have focused on achieving good electrical properties of rGO; however, it is notable that GO has potential to be used as a gate dielectric layer of OFETs since it possesses insulating properties and a very high k [18][19][20]. Nevertheless, neither the dielectric properties of GO-based materials nor their application as dielectric layers of OFETs has been studied satisfactorily. To enable the use of GO as a dielectric layer of OFETs, its surface properties need to be modified because the hydrophilic hydroxyl and epoxide functional groups on the GO surface can function as trap sites and reduce the device characteristics. Several studies have attempted to passivate the hydrophilic surface of gate dielectrics with hydrophobic polymers to realize high-performance and reliable OFETs [21,22].
Here, we report on the feasibility of using GO as the gate dielectric layer of low-voltage OFETs. We attempted to modify the surface of GO by overlaying it with the hydrophobic polymer polystyrene (PS). Through atomic force microscopy (AFM), X-ray diffraction (XRD), and two-dimensional grazing incidence X-ray diffraction (2D-GIXD) analysis, we confirmed that the GO/PS bilayer gate dielectric reduced the surface roughness and increased the crystallinity of the organic semiconductor. We also found that the GO/PS bilayer gate dielectric resulted in a reduced gate leakage current, which, in turn, drastically enhanced the electrical properties of OFETs within a low operating voltage of −5 V.

Film Characterization
GO was synthesized using the modified Hummers' method, as shown in Figure 1; further details of this synthesis have been reported in a previous paper [16]. Final dried GO flakes were dispersed in a deionized water/methanol (2:1) mixed solvent (1.5 wt %) by using a sonicator. For film characterization, GO solutions were spin-coated onto Si substrates at 1200 rpm for 60 s and cured at 120 • C for 30 min. To form the GO/PS bilayer, 0.7 wt % PS solution in toluene was spin-coated onto the GO films at 4000 rpm for 45 s, and then cured at 90 • C for 20 min. The GO and PS solutions were spin-coated in air. The film thickness was measured by ellipsometry (J.A. Woollam). The surface morphologies and C i were characterized using an atomic force microscope (MultiMode SPM, Digital Instruments Inc., Santa Barbara, CA, USA) and the HP 4284A precision LCR meter (Agilent, Santa Clara, CA, USA), respectively. To investigate the crystallinity of the organic semiconductor films, a 50 nm-thick pentacene film was deposited onto various dielectric layers (GO, GO/PS, and PS). The pentacene films were investigated via XRD and 2D-GIXD experiments, which were performed at the 10C1 and 4C2 beamlines (wavelength = 1.38 Å), respectively, at the Pohang Accelerator Laboratory in Korea. The measurements of C i and leakage current were performed using a metal-insulator-metal structure.

Device Fabrication
For the fabrication of OFETs, highly p-doped Si wafers were used as gate electrodes and substrates. After piranha cleaning and consecutive DI water washing of the substrates, the GO solutions were spin-coated onto them at 1200 rpm for 60 s and cured at 120 • C for 30 min. Then, 0.7 wt % PS solution in toluene was spin-coated onto the GO films at 4000 rpm for 45 s, and cured at 90 • C for 20 min. A 50 nm-thick pentacene film, serving as the active layer, was deposited onto the GO/PS dielectric at a rate of 0.2 Å s −1 by means of an organic molecular beam deposition system. The film deposition conditions were kept identical for the film analysis and the device. Finally, Au source/drain electrodes with a thickness of 100 nm each were deposited using a thermal evaporator (Figure 1b). Electrical measurements were conducted using Keithley 2400 and 236 source/measure units. The electrical properties were evaluated in the dark under ambient conditions. The device parameters were calculated on the basis of the transfer curves in the saturation regime by using the equation I d = (W/2L)·µ·C i ·(V g − V th ) 2 ; here, I d , µ, V g , and V th are the drain current, field-effect mobility, gate voltage, and threshold voltage, respectively; W and L are the channel width and length, respectively; and C i is the capacitance per unit area of the GO/PS gate insulator.

Device Fabrication
For the fabrication of OFETs, highly p-doped Si wafers were used as gate electrodes and substrates. After piranha cleaning and consecutive DI water washing of the substrates, the GO solutions were spin-coated onto them at 1200 rpm for 60 s and cured at 120 °C for 30 min. Then, 0.7 wt % PS solution in toluene was spin-coated onto the GO films at 4000 rpm for 45 s, and cured at 90 °C for 20 min. A 50 nm-thick pentacene film, serving as the active layer, was deposited onto the GO/PS dielectric at a rate of 0.2 Å s -1 by means of an organic molecular beam deposition system. The film deposition conditions were kept identical for the film analysis and the device. Finally, Au source/drain electrodes with a thickness of 100 nm each were deposited using a thermal evaporator ( Figure 1b). Electrical measurements were conducted using Keithley 2400 and 236 source/measure units. The electrical properties were evaluated in the dark under ambient conditions. The device parameters were calculated on the basis of the transfer curves in the saturation regime by using the equation Id = (W/2L)·μ·Ci·(Vg -Vth) 2 ; here, Id, μ, Vg, and Vth are the drain current, field-effect mobility, gate voltage, and threshold voltage, respectively; W and L are the channel width and length, respectively; and Ci is the capacitance per unit area of the GO/PS gate insulator.

Film Characterization
The surface morphologies of the synthesized GO, GO/PS bilayer, and pentacene deposited on the GO/PS bilayer were studied by AFM. Figure 1c shows the synthesized GO pieces obtained from a highly diluted solution; the pieces are in the form of flat sheet-type structures with an average sheet size of about 600 nm (with some size deviation from sheet to sheet). The inset of Figure 1c shows the height profile of a 1.5-2.0 nm GO slice, which reveals that the GO flakes are well separated by a single layer. Figures 2a,b, respectively, show the surface morphologies of the GO film (thickness of 70 nm) and PS-coated GO (GO/PS bilayer, total thickness of 75 nm) film used in this system. As can be seen in the AFM images, coating the PS layer on the GO surface can significantly reduce the surface rootmean-square (Rq) of the GO film, from 4.91 nm to 2.17 nm, and improve the uniformity. Figure 2c shows the morphology of the pentacene film deposited on the GO/PS film; the average grain size is approximately 250 nm, and Rq roughness is 7.8 nm.

Film Characterization
The surface morphologies of the synthesized GO, GO/PS bilayer, and pentacene deposited on the GO/PS bilayer were studied by AFM. Figure 1c shows the synthesized GO pieces obtained from a highly diluted solution; the pieces are in the form of flat sheet-type structures with an average sheet size of about 600 nm (with some size deviation from sheet to sheet). The inset of Figure 1c shows the height profile of a 1.5-2.0 nm GO slice, which reveals that the GO flakes are well separated by a single layer. Figure 2a,b, respectively, show the surface morphologies of the GO film (thickness of 70 nm) and PS-coated GO (GO/PS bilayer, total thickness of 75 nm) film used in this system. As can be seen in the AFM images, coating the PS layer on the GO surface can significantly reduce the surface root-mean-square (R q ) of the GO film, from 4.91 nm to 2.17 nm, and improve the uniformity. Figure 2c shows the morphology of the pentacene film deposited on the GO/PS film; the average grain size is approximately 250 nm, and R q roughness is 7.8 nm. To measure the gate dielectric properties of the GO and GO/PS bilayer films, metal-insulatormetal capacitors (herein, Au-GO-heavily p-doped Si wafer or Au-GO/PS-heavily p-doped Si wafer) were fabricated. Figure 3 shows the measured Ci and electric-field-dependent gate leakage current density. The Ci value of GO decreases from 85 to 62.4 nF cm -2 (average: 73.3 nF cm -2 ) and that of GO/PS decreases from 40.3 to 34.8 nF cm -2 (average: 37.8 nF cm -2 ), as the frequency increases from 10 kHz to 1 MHz, which agrees well with the reported Ci value of a GO film with a similar thickness To measure the gate dielectric properties of the GO and GO/PS bilayer films, metal-insulator-metal capacitors (herein, Au-GO-heavily p-doped Si wafer or Au-GO/PS-heavily p-doped Si wafer) were fabricated. Figure 3 shows the measured C i and electric-field-dependent gate leakage current density. The C i value of GO decreases from 85 to 62.4 nF cm −2 (average: 73.3 nF cm −2 ) and that of GO/PS decreases from 40.3 to 34.8 nF cm −2 (average: 37.8 nF cm −2 ), as the frequency increases from 10 kHz to 1 MHz, which agrees well with the reported C i value of a GO film with a similar thickness [13]. Although the C i value of the GO/PS bilayer is smaller than that of the GO film because of the low dielectric constant of PS, the former C i is high enough for GO/PS to serve as a dielectric layer for low-voltage operation of OFETs. As can be observed from the data in Figure 3a, the C i values of the GO film and the GO/PS bilayer decrease by about 27% and 14%, respectively, with an increase in the frequency to up to 1 MHz; this indicates that the GO/PS bilayer has fewer mobile impurities on the dielectric surface than does the GO single layer. Figure 3b shows the electric-field-dependent gate leakage current. The GO single layer shows a high leakage current (10 −4 -10 −7 A cm −2 ), whereas the gate leakage current of GO/PS bilayer is one order or more less than that of the GO film; this indicates the excellent electrical strength of the GO/PS bilayer. As mentioned in the introduction part, since the hydrophilic hydroxyl and/or epoxide functional groups on the GO surface can function as trap sites and reduce the device characteristics, it is necessary to modify the GO surface with the hydrophobic layer. The leakage current reduction can be attributed to the surface passivation of the hydrophilic GO with the hydrophobic PS, which could facilitate the use of GO as a dielectric of the OFETs. To measure the gate dielectric properties of the GO and GO/PS bilayer films, metal-insulatormetal capacitors (herein, Au-GO-heavily p-doped Si wafer or Au-GO/PS-heavily p-doped Si wafer) were fabricated. Figure 3 shows the measured Ci and electric-field-dependent gate leakage current density. The Ci value of GO decreases from 85 to 62.4 nF cm -2 (average: 73.3 nF cm -2 ) and that of GO/PS decreases from 40.3 to 34.8 nF cm -2 (average: 37.8 nF cm -2 ), as the frequency increases from 10 kHz to 1 MHz, which agrees well with the reported Ci value of a GO film with a similar thickness [13]. Although the Ci value of the GO/PS bilayer is smaller than that of the GO film because of the low dielectric constant of PS, the former Ci is high enough for GO/PS to serve as a dielectric layer for low-voltage operation of OFETs. As can be observed from the data in Figure 3a, the Ci values of the GO film and the GO/PS bilayer decrease by about 27% and 14%, respectively, with an increase in the frequency to up to 1 MHz; this indicates that the GO/PS bilayer has fewer mobile impurities on the dielectric surface than does the GO single layer. Figure 3b shows the electric-field-dependent gate leakage current. The GO single layer shows a high leakage current (10 -4 -10 -7 A cm -2 ), whereas the gate leakage current of GO/PS bilayer is one order or more less than that of the GO film; this indicates the excellent electrical strength of the GO/PS bilayer. As mentioned in the introduction part, since the hydrophilic hydroxyl and/or epoxide functional groups on the GO surface can function as trap sites and reduce the device characteristics, it is necessary to modify the GO surface with the hydrophobic layer. The leakage current reduction can be attributed to the surface passivation of the hydrophilic GO with the hydrophobic PS, which could facilitate the use of GO as a dielectric of the OFETs.

Molecular Ordering and Crystallinity
The molecular ordering and crystallinity of the pentacene layers on various dielectrics (GO, GO/PS, and PS) were investigated by out-of-plane XRD and 2D-GIXD analysis. Figure 4 shows the XRD patterns of the GO film and pentacene films on the various dielectrics. As can be seen from the black and blue graphs in Figure 4, the diffraction peaks of the GO film correspond to (001) and (002) planes, and an interlayer spacing (d 001 ) of 8.3 ± 0.1 Å, and the diffraction peaks of the pentacene layer on the PS substrate correspond to (001), (002), and (003) planes with d 001 of 15.5 ± 0.1 Å; these results are in good agreement with literature values [23,24]. Diffraction peaks of only GO are observed in the XRD patterns of pentacene on the GO film; on the other hand, in the XRD patterns of pentacene on the GO/PS bilayer film, thin-film-phase diffraction peaks of pentacene are observed, as seen in Figure 4. This indicates that the pentacene film is more ordered and has more aligned crystalline on the GO/PS bilayer film than on the GO film. on the PS substrate correspond to (001), (002), and (003) planes with d001 of 15.5 ± 0.1 Å; these results are in good agreement with literature values [23,24]. Diffraction peaks of only GO are observed in the XRD patterns of pentacene on the GO film; on the other hand, in the XRD patterns of pentacene on the GO/PS bilayer film, thin-film-phase diffraction peaks of pentacene are observed, as seen in Figure 4. This indicates that the pentacene film is more ordered and has more aligned crystalline on the GO/PS bilayer film than on the GO film. Since the crystal structure of organic semiconductors affects the carrier transport properties, analysis of the crystal structures of thin-film organic semiconductors is crucial for understanding the electrical and physical properties of OFETs. Figure 5 shows 2D-GIXD scan images of the GO film and pentacene films deposited on the various dielectrics. In Figure 5a, a broad (001) plane of GO is observed in the qz direction (direction parallel to the substrate), which corresponds to the XRD result of GO in Figure 4. The 2D-GIXD patterns of pentacene in Figures 5b,c reveal that the pentacene film on the GO dielectric contains both a "thin-film phase" and a "bulk phase" in the qz and qxy directions, whereas the pentacene film on the GO/PS bilayer shows a relatively highly oriented "thin-film phase" in the qz and qxy directions. In the case of carrier transport in pentacene, the π-π overlap depends largely on the molecular alignment along the in-plane direction, qxy, and not the out-of-plane direction, qz. It has been reported that the bulk phase corresponds to a tilted molecular orientation and the poorest degree of π-π overlap [25]. Therefore, the 2D-GIXD results indicate that the pentacene grains are well-stacked with fewer mismatched and tilted crystalline domains on the GO/PS bilayer than on the GO film. Since the crystal structure of organic semiconductors affects the carrier transport properties, analysis of the crystal structures of thin-film organic semiconductors is crucial for understanding the electrical and physical properties of OFETs. Figure 5 shows 2D-GIXD scan images of the GO film and pentacene films deposited on the various dielectrics. In Figure 5a, a broad (001) plane of GO is observed in the q z direction (direction parallel to the substrate), which corresponds to the XRD result of GO in Figure 4. The 2D-GIXD patterns of pentacene in Figure 5b,c reveal that the pentacene film on the GO dielectric contains both a "thin-film phase" and a "bulk phase" in the q z and q xy directions, whereas the pentacene film on the GO/PS bilayer shows a relatively highly oriented "thin-film phase" in the q z and q xy directions. In the case of carrier transport in pentacene, the π-π overlap depends largely on the molecular alignment along the in-plane direction, q xy , and not the out-of-plane direction, q z . It has been reported that the bulk phase corresponds to a tilted molecular orientation and the poorest degree of π-π overlap [25]. Therefore, the 2D-GIXD results indicate that the pentacene grains are well-stacked with fewer mismatched and tilted crystalline domains on the GO/PS bilayer than on the GO film.
Appl. Sci. 2018, 8, x FOR PEER REVIEW 6 of 8 Figure 5. Two-dimensional grazing incidence X-ray diffraction (2D-GIXD) scan images of (a) GO film, (b) pentacene films deposited on GO, and (c) GO/PS dielectric. Subscripts "T" and "B" represent "thin-film phase" and "bulk phase," respectively. Figure 6a shows the transfer characteristics in the saturation regime (VD = −5 V) for a pentacene-based OFET with a GO/PS bilayer dielectric (W/L = 1000/100 μm). In the case of OFET device, using GO as a dielectric layer, the transistor characteristics were not shown despite the high Ci value of GO film, which is due to the high surface roughness and high leakage of GO film, and the poor crystallinity of pentacene on the GO dielectric. By contrast, the OFET with the GO/PS bilayer dielectric exhibits a high μ of 1.05 cm 2 V -1 s -1 , an on/off ratio exceeding 10 2 , and Vth of −1.4 V with Ci of 37.8 nF cm -2 . Figure 6b shows the output characteristics (ID vs. VD curves at VG = 0, −1.25, −2.5, −3.75, and −5 V) of the OFET with the GO/PS bilayer dielectric. Although the OFET shows some leakage current at VG = 0 V, the device can be operated within −5 V with Figure 5. Two-dimensional grazing incidence X-ray diffraction (2D-GIXD) scan images of (a) GO film, (b) pentacene films deposited on GO, and (c) GO/PS dielectric. Subscripts "T" and "B" represent "thin-film phase" and "bulk phase," respectively. Figure 6a shows the transfer characteristics in the saturation regime (V D = −5 V) for a pentacene-based OFET with a GO/PS bilayer dielectric (W/L = 1000/100 µm). In the case of OFET device, using GO as a dielectric layer, the transistor characteristics were not shown despite the high C i value of GO film, which is due to the high surface roughness and high leakage of GO film, and the poor crystallinity of pentacene on the GO dielectric. By contrast, the OFET with the GO/PS bilayer dielectric exhibits a high µ of 1.05 cm 2 V −1 s −1 , an on/off ratio exceeding 10 2 , and V th of −1.4 V with C i of 37.8 nF cm −2 . Figure 6b shows the output characteristics (I D vs. V D curves at V G = 0, −1.25, −2.5, −3.75, and −5 V) of the OFET with the GO/PS bilayer dielectric. Although the OFET shows some leakage current at V G = 0 V, the device can be operated within −5 V with clear saturation behavior. It is not easy to fabricate reproducible OFET devices (yield less than 50 %), however, this study successfully enabled the use of GO as a dielectric layer of low-voltage OFET with a high mobility. Figure 6a shows the transfer characteristics in the saturation regime (VD = −5 V) for a pentacene-based OFET with a GO/PS bilayer dielectric (W/L = 1000/100 μm). In the case of OFET device, using GO as a dielectric layer, the transistor characteristics were not shown despite the high Ci value of GO film, which is due to the high surface roughness and high leakage of GO film, and the poor crystallinity of pentacene on the GO dielectric. By contrast, the OFET with the GO/PS bilayer dielectric exhibits a high μ of 1.05 cm 2 V -1 s -1 , an on/off ratio exceeding 10 2 , and Vth of −1.4 V with Ci of 37.8 nF cm -2 . Figure 6b shows the output characteristics (ID vs. VD curves at VG = 0, −1.25, −2.5, −3.75, and −5 V) of the OFET with the GO/PS bilayer dielectric. Although the OFET shows some leakage current at VG = 0 V, the device can be operated within −5 V with clear saturation behavior. It is not easy to fabricate reproducible OFET devices (yield less than 50 %), however, this study successfully enabled the use of GO as a dielectric layer of low-voltage OFET with a high mobility.

Conclusions
In summary, we have successfully demonstrated a high-performance OFET with a GO/PS bilayer gate dielectric, which shows μ of 1.05 cm 2 V -1 s -1 and operates within a low voltage of −5 V. The high performance of the device is attributed to the significant reduction in the surface roughness and gate leakage current through overlaying of the hydrophilic GO surface with hydrophobic PS, as

Conclusions
In summary, we have successfully demonstrated a high-performance OFET with a GO/PS bilayer gate dielectric, which shows µ of 1.05 cm 2 V −1 s −1 and operates within a low voltage of −5 V. The high performance of the device is attributed to the significant reduction in the surface roughness and gate leakage current through overlaying of the hydrophilic GO surface with hydrophobic PS, as well as to a significant increase in the crystallinity of the pentacene film on the GO/PS bilayer surface. We believe that this work provides a facile route for fabricating low-power-consumption electronic devices by taking advantage of the thinness and excellent insulating properties of GO, which have not been satisfactorily studied in the past.

Conflicts of Interest:
The authors declare no conflict of interest.