5GHz CMOS All-Pass Filter-Based True Time Delay Cell

Analog CMOS time-delay cells realized by passive components, e.g., lumped LC delay lines, are inefficient in terms of area for multi-GHz frequencies. All-pass filters considered as active circuits can, therefore, be the best candidates to approximate time delays. This paper proposes a broadband first-order voltage-mode all-pass filter as a true-time-delay cell. The proposed true-time-delay cell is capable of tuning delay, demonstrating its potential capability to be used in different systems, e.g., RF beam-formers. The proposed filter achieves a flat group delay of over 60 ps with a pole/zero pair located at 5 GHz. This proposed circuit consumes only 10 mW power from a 1.8-V supply. To demonstrate the performance of the proposed all-pass filter, simulation results are conducted by using Virtuoso Cadence in a standard TSMC 180-nm CMOS process.


Introduction
All-pass filters as delay cells have a variety of applications in signal processing and communication systems, like equalizers and analog/RF beam-formers [1][2][3][4][5][6]. In these circuits, the amplitude of the input signal is constant over the desired frequency band, while creating a frequency-dependent delay. There are several reported approaches to approximately realize delay, such as transmission lines and lumped LC delay lines [7,8], which are passive components and, thus, are area inefficient, and also phase shifters for narrow-band frequencies [9][10][11][12][13][14]. Apart from these circuits, an active RF all-pass filter can be the best option to approximate delay due to its size and delay to area ratio [15,16].
There are many voltage-mode all-pass filters reported over the last one decade, which operate in broadband frequencies and have different applications [15][16][17][18][19][20][21]. In some applications, e.g., RF beam-forming, delay stages as delay cells are normally realized by cascading first-order all-pass filters in order to achieve a desired delay [15][16][17]. However, there are just a few first-order voltage-mode all-pass filters for wide frequency ranges in the literature [15][16][17]22]. This is because these analog circuits should possess important specifications like wide bandwidth, efficient area, low cost, and power consumption, and high delay amount to be considered as practical and efficient systems. Furthermore, recent circuits have been taking advantage of tunability, since it is one of the key features of signal processing and communication systems [15,16,18,23].
A broadband first-order voltage-mode all-pass filter as a true-time-delay cell is introduced in this paper. The proposed all-pass filter is comprised of two transistors, two resistors, and one grounded inductor. This circuit demonstrates a large amount of delay in a single delay cell through a wide frequency band. The amount of delay can be controlled within the frequency range of interest. Moreover, circuit optimization is carried out to increase the operating frequency and improve the performance of the filter, in particular, in high frequencies.
The structure of this paper is as follows: Section 2 describes the structure of proposed all-pass filter and provides theoretical analyses. In Section 3, circuit optimization technique and tunability are presented, and also the parasitic effects of the proposed filter are evaluated. Section 4 provides results and ultimately a discussion is provided in Section 5. Figure 1 shows the block level of the first-order voltage-mode all-pass filter. As shown, a first-order all-pass filter can be approximated by the combination of two sections: a low-pass section with a DC gain of 2 and a unity gain section [24]. Therefore, its ideal transfer function is given as:

Proposed First-Order All-Pass Filter
where τ is the time delay. Ideally, the gain of the transfer function is 1 and its phase is linear versus the frequency.  Figure 2 illustrates the block diagram and schematic of the proposed broadband first-order voltage-mode all-pass filter. In this filter, transistor M 1 , inductor L, and resistor R L form the low-pass part, while transistor M 2 and resistor R L comprise the unity-gain part. In other words, M 1 and M 2 are, respectively, common-source (CS) and common-gate (CG) configurations to convert the input voltage signal into current. At the output node, the drain currents of M 1 and M 2 are subtracted to realize an all-pass function. Then, the output signal will be converted back to voltage by the load resistor R L . Ignoring the parasitics of the transistors (the parasitic effects will be assessed in Section 3) for simplicity, the transfer function of the proposed first-order all-pass filter can be determined by: where g m1 and g m2 are the transconductances of M 1 and M 2 , respectively. If g m1 = 2g m2 and g m2 R L = 1, an all-pass structure will be realized with the same frequency of the left-plane pole and right-plane zero, resulting in twice the phase and group delay responses of an all-pass circuit. As a consequence, the transfer function in (2) can be simplified as: The pole/zero frequency and phase response of the first-order all-pass filter can be given as: respectively, and, thus, group delay response is expressed by: where ω is the angular frequency related to the frequency f through ω = 2π f . The group delay is approximately equal to 2Lg m1 at low frequencies. However, this group delay is practically affected by parasitic inductances stemmed from, e.g., bonding wire and PCB and, thus, its value will be increased. The input impedance of the proposed all-pass filter can be simply approximated by considering the Miller effect on the parasitic capacitances of the transistor M 1 plus C gs2 given as: which its value affects the next delay stage for cascading purposes.

Circuit Optimization and Tunability
In order to contribute to the linearity and increase the operating frequency of the proposed all-pass filter, a variable resistor (R d ) is added to the unity-gain path as shown in Figure 3. In this case, a discrete tuning of delay can be carried out by changing the value of R d and the bias voltage of M 2 as well, which adjusts g m2 . The R d can be implemented by a switched resistors bank which can be implemented by CMOS transistors, with great ease.
The transfer function of the CG transistor of M 2 (the part inside the dotted box) is, therefore, given as: Its value for low and high frequencies is H CG,LF ≈ g m2 R L and H CG,HF ≈ g m2 R L /C gd2 (R L + R d ), respectively. Hence, the R d will affect the frequency response of the proposed filter at higher frequencies. Note that g m2 R L (i.e., the unity gain section) is no longer equal to 1 at high frequencies, but via varying the bias voltage of M 2 , g m2 changes and, therefore, the two conditions g m1 = 2g m2 and g m2 R L = 1 will be satisfied.

Non-Ideality Analysis
To analyze accurately the performance of the proposed all-pass filter in Figure 3 at high frequencies, the finite output impedances (g ds ) and parasitic capacitances (C gs and C gd ) of the transistors M 1 and M 2 should be considered. Therefore, the transfer function in (2) can be rewritten as: If g m1,2 g ds1,2 , g ds1,2 R L 1, and g ds2 R d 1, the transfer function in Equation (9) can be simplified as: which includes additional parasitic poles and zero. These parasitic high-frequency poles stemmed from C gd1 and C gd2 , which are located at 1/C gd1 R L and 1/C gd2 (R L + R d ) respectively, are far beyond the dominant pole in Equation (4) since the values of R L and R d are small. Moreover, the additional right-plane zero (g m1 /Lg m1 g ds1 + C gd1 ) is located at considerably higher frequencies, as well. Additionally, small-signal analysis conducted on the proposed all-pass circuit indicates that the third parasitic pole stemmed from C gs1 will be located at: which is far beyond the dominant pole in Equation (4). It can be noted that the order of the proposed circuit will increase and convert to the second one if the absolute value of C gs1 , which is process-dependent, is large enough. Consequently, choosing an appropriate CMOS process can reduce the effect of the C gs1 on the frequency response of the circuit.

Results
The proposed first-order all-pass filter is designed in a standard 180-nm TSMC CMOS process and results are obtained using Virtuoso Cadence. The proposed all-pass filter is simulated without and with the R d . The power consumption of the proposed broadband true-time-delay cell is only 10 mW from a 1.8-V supply voltage. Figure 4 shows the gain and phase responses of the proposed filter under different values of the R d . As it can be observed, the gain of the proposed filter without the R d (i.e., R d = 0 Ω) is almost −0.5 dB due to the existence of the parasitic capacitors and finite output impedances of the transistors. Furthermore, the proposed filter does not achieve desired (flat) gain responses at higher frequencies, whereas by varying the value of the R d , better gain responses are proved at these frequencies. As seen, the pole/zero frequency of the proposed circuit with R d = 120 Ω is 5 GHz (i.e., the point where phase is 90 • ), indicating a 14% bandwidth improvement compared to once R d = 0 Ω (i.e., 4.4 GHz). The group delay responses of the proposed all-pass filter for different values of the R d are shown in Figure 5. As it can be seen, the delay can be controlled by varying the R d . The group delay is equal to about 59 ps, when R d = 120 Ω. This group delay value is very close to the theoretical one in Equation (6), with an error of around 11%. In Figure 6, the input-referred noise response of the all-pass filter is shown when R d = 120 Ω. The input-referred noise value is approximately 2.36 nV/sqrt (Hz) by the frequency of 1 GHz. Figure 7 shows the noise figure of the proposed all-pass filter with R d = 120 Ω, which is <15 dB over the frequency band. The input-referred 1-dB compression point (P 1dB ) and input-referred third-order intercept point (IIP3) responses of the first-order all-pass filter with R d = 120 Ω are shown in Figure 8. The input-referred P 1dB and IIP3 are −1.9 dBm and 16.6 dBm at 2.5 GHz, respectively.   Since the amount of group delay is affected by the mismatch and is basically process, voltage, and temperature (PVT) dependent, we should therefore consider the effect of these variations on the proposed true-time-delay cell. Figure 9 illustrates Monte Carlo simulation results, which are performed with a Gaussian distribution and 100 iterations, when R d = 120 Ω. As it can be seen, the difference between group delay responses due to the mismatch is very small. Although the gain, P 1dB , and IIP3 will be affected by the mismatch, these variations can be minimized by changing the bias voltage of M 2 . The group delay responses of the proposed filter with R d = 120 Ω for different supply voltages and temperatures are shown in Figure 10. The delay degrades by 15% because of the temperature variations.  A comparison between recently reported voltage/current all-pass filters and the proposed true-time-delay cell is presented in Table 1. Comparing the results of the first-order voltage-mode all-pass filters, the proposed filter has improved the frequency range compared to the filter in [15]. Moreover, the power consumption and delay tuning can be highlighted and compared with the filter in [22], in which the delay could not be tuned.

Discussion
Compared to the bulky LC delay lines, active filters can be good alternatives to approximate delays as these filters occupy smaller area. This paper presents a broadband first-order voltage-mode all-pass filter as an active circuit. Via an optimization technique, 14% bandwidth extension is achieved. The proposed first-order all-pass filter demonstrates a flat group delay of approximately 60ps through a bandwidth of 5 GHz, while consuming merely 10 mW power. Unlike the active all-pass filter in [22], the proposed filter has a DC-gain of 1 in its voltage transfer function and consequently there is no need for the gain adjustment via additional circuits or components. Furthermore, the proposed circuit proves a frequency range wider than that of the reported active filter in [15] (pre-layout pole frequency of 2.63 GHz), however at a larger area. The proposed all-pass filter is almost linear and achieves the input-referred P 1dB of −1.9 dBm and the input-referred IIP3 of 16.6 dBm. We will employ the proposed all-pass filter-based true-time-delay cell in analog RF beam-forming antennas for communication applications in our future work (see Figure 11). In timed-array receivers, tunable true-time-delay cells are exploited to align broadband signals received from a particular direction (θ).