Dual-Input Isolated DC-DC Converter with Ultra-High Step-Up Ability Based on Sheppard Taylor circuit

A dual-input high step-up isolated converter (DHSIC) is proposed in this paper, which incorporates Sheppard Taylor circuit into power stage design so as to step up voltage gain. In addition, the main circuit adopts boosting capacitors and switched capacitors, based on which the converter voltage gain can further be improved significantly. Since the proposed converter possesses an inherently ultra-high step-up feature, it is capable of processing low input voltages. The DHSIC also has the important features of leakage energy recycling, switch voltage clamping, and continuous input-current obtaining. These characteristics advantage converter efficiency and benefit the DHSIC for high power applications. The structure of the proposed converter is concise. That is, it can lower cost and simplifies control approach. The operation principle and theoretical derivation of the proposed converter are discussed thoroughly in this paper. Simulations and hardware implementation are carried out to verify the correctness of theoretical analysis and to validate feasibility of the converter as well.


Introduction
Nowadays, electricity is mostly generated by fossil fuels and nuclear fuel. Although nuclear power plants can generate considerable power by utilizing a little amount of nuclear fuel, nuclear waste influencing the environment is inevitable. Fossil fuels have been overused and become in shortage. Therefore, human beings attempt to discover more alternatives for maintaining global economic development and environment protection. To alleviate the problems of global temperature rising and serious greenhouse gas emission, many kinds of clean-energy power generation, such as photovoltaic (PV) panel, wind turbine, and fuel-cell stack, are developed imperatively [1,2].
In general, renewable power systems need a DC-bus voltage in the range of 380 V-400 V for grid-tied connection or in high power applications. Unfortunately, the output voltage of a PV module, battery or fuel cell is much lower than the dc-bus voltage and thus conventional DC/DC converters cannot be utilized directly to serve as an energy interface for dealing with power control. In addition, if the power supplied from two input ports has to be processed simultaneously, dual-input converter with high voltage gain is essentially anticipated. Figure 1 illustrates a hybrid generation system that includes two sources, a high step-up converter, and an inverter for AC application, which reveals that a dual-input converter with high step-up voltage gain is urgent in such system. Theoretically, conventional step-up converters, like Boost and Flyback [3][4][5][6], can achieve a high voltage gain under the operating with extremely high duty ratio or the design of a much higher turns ratio. However, extreme high duty cycle or turns ratio will dramatically degrade the conversion efficiency due to large conduction loss and copper loss of windings. In order to improve conversion efficiency and voltage gain, many transformerless high step-up converters are proposed [7][8][9][10]. Although these converters are designed to achieve high step-up characteristics with reasonable duty ratio, here still exits some problems, for instance, large transient current and limited voltage gain, confining converter flexibility. To mitigate the mentioned drawbacks, converters incorporating coupled inductor and/or switched capacitor are proposed [11][12][13][14], however, which are only able to process single-input source. In order to deal with two different kinds of inputs, dual-input converters (DIC) are proposed. In comparison with single input, a dual generation system is capable of providing higher reliability, durability and power rating. The structure of DICs can be simply classified as series type and parallel one. The conventional series-type DICs construct string connection at input ports [15,16]. Such a DIC will malfunction in case that either of the two inputs fails. The parallel-type DICs collocate different sources in parallel so that even if one of the inputs is out of commitment, it still can accomplish voltage stepping to meet DC-bus level [17][18][19][20][21][22][23]. Some of them are controlled with time-sharing scheme. That is, only one DC source is permitted to delivery its energy to the load at a time. Compared with series-type DICs, parallel ones possess much better features from the aspects of reliability and controllability. Nevertheless, limitation on voltage gain is unavoidable, which confines converter applications in the field of high DC-bus voltage requirement.
In order to convert a lower DC voltage to a much higher level and to provide consecutive power even under the situation that one input source shuts down, this paper proposes a DHSIC, which is developed by means of boosting capacitor, switched capacitor and Sheppard Taylor circuit. The proposed dual-input converter can achieve the following important features: ultra-high step-up ability, continuous input current, and galvanic isolation. Furthermore, the proposed converter possesses the competence of inherent voltage clamping without any additional devices and recycling leakage energy stored in transformers. Therefore, the voltage spike on the power switch can be suppressed and converter efficiency is also improved.
The structure of this paper is organized as follows. Following the introduction, the operation principle of the proposed dual-input high step-up isolated converter is described in Section 2. The steady-state analysis is discussed in Section 3, which covers voltage gain of the converter, voltage and current stresses of the semiconductor device, and magnetizing inductance design in continuous conduction mode (CCM). To verify the correctness of proposed converter, experimental results from a 200-W prototype are illustrated in Section 4. Finally, Section 5 summarizes the conclusions of this paper. Theoretically, conventional step-up converters, like Boost and Flyback [3][4][5][6], can achieve a high voltage gain under the operating with extremely high duty ratio or the design of a much higher turns ratio. However, extreme high duty cycle or turns ratio will dramatically degrade the conversion efficiency due to large conduction loss and copper loss of windings. In order to improve conversion efficiency and voltage gain, many transformerless high step-up converters are proposed [7][8][9][10]. Although these converters are designed to achieve high step-up characteristics with reasonable duty ratio, here still exits some problems, for instance, large transient current and limited voltage gain, confining converter flexibility. To mitigate the mentioned drawbacks, converters incorporating coupled inductor and/or switched capacitor are proposed [11][12][13][14], however, which are only able to process single-input source. In order to deal with two different kinds of inputs, dual-input converters (DIC) are proposed. In comparison with single input, a dual generation system is capable of providing higher reliability, durability and power rating. The structure of DICs can be simply classified as series type and parallel one. The conventional series-type DICs construct string connection at input ports [15,16]. Such a DIC will malfunction in case that either of the two inputs fails. The parallel-type DICs collocate different sources in parallel so that even if one of the inputs is out of commitment, it still can accomplish voltage stepping to meet DC-bus level [17][18][19][20][21][22][23]. Some of them are controlled with time-sharing scheme. That is, only one DC source is permitted to delivery its energy to the load at a time. Compared with series-type DICs, parallel ones possess much better features from the aspects of reliability and controllability. Nevertheless, limitation on voltage gain is unavoidable, which confines converter applications in the field of high DC-bus voltage requirement.

Operation Principle of Proposed Dual-Input Converter
In order to convert a lower DC voltage to a much higher level and to provide consecutive power even under the situation that one input source shuts down, this paper proposes a DHSIC, which is developed by means of boosting capacitor, switched capacitor and Sheppard Taylor circuit. The proposed dual-input converter can achieve the following important features: ultra-high step-up ability, continuous input current, and galvanic isolation. Furthermore, the proposed converter possesses the competence of inherent voltage clamping without any additional devices and recycling leakage energy stored in transformers. Therefore, the voltage spike on the power switch can be suppressed and converter efficiency is also improved.
The structure of this paper is organized as follows. Following the introduction, the operation principle of the proposed dual-input high step-up isolated converter is described in Section 2. The steady-state analysis is discussed in Section 3, which covers voltage gain of the converter, voltage and current stresses of the semiconductor device, and magnetizing inductance design in continuous conduction mode (CCM). To verify the correctness of proposed converter, experimental results from a 200-W prototype are illustrated in Section 4. Finally, Section 5 summarizes the conclusions of this paper.

Operation Principle of Proposed Dual-Input Converter
The equivalent of the proposed DHSIC is shown in Figure 2. Parameters in Figure 2 are represented in the following. V in1 and V in2 are input voltages, while i in1 and i in2 denote input currents. The practical model of coupled inductor includes magnetizing inductance, leakage inductance, and an ideal transformer. The L m1 and L m2 are the magnetizing inductances of T 1 and T 2 , respectively, meanwhile, leakage inductances are expressed as L k1 and L k2 . The S 1 -S 4 represent the four main power switches. The C 1 and C 2 function as boosting capacitors, and C 3 and C 4 serve as switched capacitors. These capacitors can elevate converter voltage gain effectively. The D 1 -D 6 are rectifier diodes. In addition, D o and C o are the output diode and filter capacitor, respectively. Output voltage and current of DHSIC are in turn described as V o and I o . Finally, the output equivalent resistance is presented as R o . Even though the proposed DHSIC works normally in dual input operation (DIO), it still possesses the ability to be in single-input operation (SIO) while either input source fails. In Section 2, DIO will be first discussed followed by SIO. The equivalent of the proposed DHSIC is shown in Figure 2. Parameters in Figure 2 are represented in the following. Vin1 and Vin2 are input voltages, while iin1 and iin2 denote input currents. The practical model of coupled inductor includes magnetizing inductance, leakage inductance, and an ideal transformer. The Lm1 and Lm2 are the magnetizing inductances of T1 and T2, respectively, meanwhile, leakage inductances are expressed as Lk1 and Lk2. The S1-S4 represent the four main power switches. The C1 and C2 function as boosting capacitors, and C3 and C4 serve as switched capacitors. These capacitors can elevate converter voltage gain effectively. The D1-D6 are rectifier diodes. In addition, Do and Co are the output diode and filter capacitor, respectively. Output voltage and current of DHSIC are in turn described as Vo and Io. Finally, the output equivalent resistance is presented as Ro. Even though the proposed DHSIC works normally in dual input operation (DIO), it still possesses the ability to be in single-input operation (SIO) while either input source fails. In Section 2, DIO will be first discussed followed by SIO. Figure 2. Equivalent circuit of the proposed converter.

Dual-Input Operation
The switches S1 and S2 are turned on/off simultaneously, so do the switches S3 and S4. Assume that the turn-on period of S1 and S2 is D1Ts and D2Ts is for S3 and S4. In addition, the magnitude of Vin2 is twice that of Vin1. While the proposed DHSIC operates at DIO and in continuous conduction mode (CCM), converter operation over one switching cycle can be divided into six states. Converter operation will be described state by state as the following proceeds with. In addition, the equivalent of each state and conceptual waveforms are depicted in Figures 3 and 4

Dual-Input Operation
The switches S 1 and S 2 are turned on/off simultaneously, so do the switches S 3 and S 4 . Assume that the turn-on period of S 1 and S 2 is D 1 T s and D 2 T s is for S 3 and S 4 . In addition, the magnitude of V in2 is twice that of V in1 . While the proposed DHSIC operates at DIO and in continuous conduction mode (CCM), converter operation over one switching cycle can be divided into six states. Converter operation will be described state by state as the following proceeds with. In addition, the equivalent of each state and conceptual waveforms are depicted in Figures 3 and 4, respectively.
• State 1 [t 0~t1 ]: Converter operation begins at this state, in which all switches S 1 -S 4 are turned on at t = t 0 . All diodes are reverse except the output diode D o . The currents of leakage inductances, i Lk1 and i Lk2 , increase linearly and steeply. Meanwhile, the energy stored in magnetizing inductances L m1 and L m2 is released to the output via transformers and diode D o . When leakage inductance current rises to be equal to magnetizing current, the diode current flowing through D o will drop to zero and then this state ends. The diode D o turns OFF under zero current transition. That is, the reverse-recovery problem at D o can be therefore overcome. • State 2 [t 1~t2 ]: In State 2, the switches S 1 -S 4 remain ON. The diodes D 1 -D 4 and D o are reversely biased, but diodes D 5 and D 6 are forwarded. In this time interval, leakage inductance and magnetizing inductance of the coupled inductor T 1 absorb energy from V in1 and C 1 , similarly, L k2 and L m2 of T 2 from V in1 and C 1 . The voltage across T r1 is V in1 + V C1 and T r2 is V in2 + V C2 . At the secondary of the DHSIC, switched capacitors C 3 and C 4 are charged by the energy from coupled inductors T r1 and T r2 , respectively. This state lasts for a time interval much longer than that of State 2 and is a major state in the converter operation. • State 3 [t 2~t3 ]: During the period from t 2 to t 3 , switches S 1 and S 2 continue conducting. On the contrary, S 3 and S 4 are turned off at t 2 . The diodes D 1 -D 4 and D o are reversely biased, but D 5 and D 6 are in a forward state. The parasitic capacitances of S 3 and S 4 are charged and current i Lk2 decreases dramatically. As the increasing voltages blocked by S 3 and S 4 reach V C2 , diodes D 3 and D 4 become forwarded and then the operation state enters State 4. • State 4 [t 3~t4 ]: All active switches remain the same on-off conditions as in State 3. That is, S 1 and S 2 are closed but S 3 and S 4 open. The voltage V in1 + V C1 will supply T r1 and forwards the energy to charge switched capacitor C 3 . Meanwhile, the capacitor C 2 absorbs energy from V in2 and T r2 . Leakage energy of L k2 is recycled to C 2 . The voltage stress of S 3 and S 4 will be clamped to V C2 . This operation state ends at the time both switches S 1 and S 2 are turned off. • State 5 [t 4~t5 ]: After S 1 and S 2 are turned off, the voltage across both switches increases. At the same time, their parasitic capacitances are charging toward the value of V C1 . With respect to the other switches, S 3 and S 4 are still in the OFF state. Once parasitic capacitance-voltage approaches to V C1 , State 5 ends and blocking voltage of S 1 and S 2 will be clamped at V C1 . The switched capacitor C 3 is still charging. During the time interval of State 5, the current flowing through L k1 drops steeply. The diodes D 1 and D 2 will be forwarded at t = t 5 and then this state ends. • State 6 [t 5~t6 ]: From t 5 to t 6 , all switches remain OFF. The L m1 pumps its stored energy to charge C 1 and to the output as well. With respect to L m2 , it is also in energy-releasing but charges toward C 2 , meanwhile, part of its energy will be transformed to the secondary of T r2 to power the output. The leakage energy stored in T r1 and T r2 will be recycled to capacitors C 1 and C 2 , respectively. During State 6, the series voltage of T r1 , C 3 , T r2 , and C 4 is connected to the output. That is, the output can accordingly obtain a high voltage level. Like State 2 and 4, State 6 also plays a major role in the converter operation. While switches S 1 -S 4 are turned on again at t = t 6 , this state ends and converter operation over one switching cycle is completed.

Single-Input Operation
Once one of the inputs fails to supply power, the proposed converter still can function as a high step-up feature. Suppose that only V in1 powers the DHSIC and in CCM condition. The converter will have four operation states over switching cycle. The corresponding key waveforms and equivalent circuits are illustrated in Figures 5 and 6 in turn.
• State 1 [t 0~t1 ]: If only V in1 supplies the converter, power processing is controlled by switches S 1 and S 2 . Both switches are turned on at t = t 0 and converter operation begins. As shown in Figure 6a, the voltage across T r1 will be equal to the series voltage of C 1 and V in1 . Magnetizing inductance L m1 pumps its stored energy to the secondary of T r1 . Therefore, the current flowing through L m1 decreases. The current i Lk1 increases quickly. When i Lk1 is equal to i Lm1 , this state ends. At this time, the current flowing through the diodes D o and D 6 also drops to zero. That is, the reverse-recovery problem of both diodes is therefore resolved. • State 2 [t 1~t2 ]: The equivalent of State 2 is illustrated in Figure 6b, in which the switches S 1 and S 2 remain closed. The L m1 absorbs energy form V in1 and C 1 and thus i Lm1 increases linearly. At the secondary of T r1 , the switched capacitor C 3 is charging continuously over this stage. State 2 is a major state in the converter operation at SIO. At time t = t 2 , the switches S 1 and S 2 are turned off and then the converter operation enters the next stage. • State 3 [t 2~t3 ]: In State 2, all diodes are in reverse bias except D 5 . The parasitic capacitance of power switches S 1 and S 2 are charged and the current i Lm1 decreases. The blocking voltage of S 1 and S 2 is therefore increasing. The associated equivalent is shown in Figure 6c. When the voltage across S 1 and S 2 approaches to V C1 , diodes D 1 and D 2 become forwarded. Then, State 4 starts.
• State 4 [t 3~t4 ]: The equivalent circuit refers to Figure 6d, in which the magnetizing inductance forwards its stored energy to charge capacitor C 1 and to the output via the ideal transformer. Meanwhile, the leakage energy of L k1 is recycled to C 1 , which also suppresses the voltage spike on the active switches. Over the time interval from t 3 to t 4 , switches S 1 and S 2 are open. With respect to diode, the D 5 is in reverse state but D 1 , D 2 , D 6 and D o are forward biased. State 4 is also a major state similar to State 2, dominating the converter operation. Both switches S 1 and S 2 will be turned on again at t = t 4 and then this state ends. Converter operation over one switching cycle is completed.
Leakage energy of Lk2 is recycled to C2. The voltage stress of S3 and S4 will be clamped to VC2. This operation state ends at the time both switches S1 and S2 are turned off. • State 5 [t4~t5]: After S1 and S2 are turned off, the voltage across both switches increases. At the same time, their parasitic capacitances are charging toward the value of VC1. With respect to the other switches, S3 and S4 are still in the OFF state. Once parasitic capacitance-voltage approaches to VC1, State 5 ends and blocking voltage of S1 and S2 will be clamped at VC1. The switched capacitor C3 is still charging. During the time interval of State 5, the current flowing through Lk1 drops steeply. The diodes D1 and D2 will be forwarded at t = t5 and then this state ends. • State 6 [t5~t6]: From t5 to t6, all switches remain OFF. The Lm1 pumps its stored energy to charge C1 and to the output as well. With respect to Lm2, it is also in energy-releasing but charges toward C2, meanwhile, part of its energy will be transformed to the secondary of Tr2 to power the output. The leakage energy stored in Tr1 and Tr2 will be recycled to capacitors C1 and C2, respectively. During State 6, the series voltage of Tr1, C3, Tr2, and C4 is connected to the output. That is, the output can accordingly obtain a high voltage level. Like State 2 and 4, State 6 also plays a major role in the converter operation. While switches S1-S4 are turned on again at t = t6, this state ends and converter operation over one switching cycle is completed.

Single-Input Operation
Once one of the inputs fails to supply power, the proposed converter still can function as a high step-up feature. Suppose that only Vin1 powers the DHSIC and in CCM condition. The converter will have four operation states over switching cycle. The corresponding key waveforms and equivalent circuits are illustrated in Figures 5 and 6 in turn.
• State 1 [t0~t1]: If only Vin1 supplies the converter, power processing is controlled by switches S1 and S2. Both switches are turned on at t = t0 and converter operation begins. As shown in Figure  6a, the voltage across Tr1 will be equal to the series voltage of C1 and Vin1. Magnetizing inductance Meanwhile, the leakage energy of Lk1 is recycled to C1, which also suppresses the voltage spike on the active switches. Over the time interval from t3 to t4, switches S1 and S2 are open. With respect to diode, the D5 is in reverse state but D1, D2, D6 and Do are forward biased. State 4 is also a major state similar to State 2, dominating the converter operation. Both switches S1 and S2 will be turned on again at t = t4 and then this state ends. Converter operation over one switching cycle is completed.

Steady-State Analysis of Proposed Converter
The voltage ratio of output to input, voltage stress and current stress of the semiconductor device, and magnetizing inductance design will be covered in this section. To simplify the steadystate analysis, the following assumptions are made. 1. The values of the boosting capacitors C1 and C2 are large enough so as to keep their across

Steady-State Analysis of Proposed Converter
The voltage ratio of output to input, voltage stress and current stress of the semiconductor device, and magnetizing inductance design will be covered in this section. To simplify the steady-state analysis, the following assumptions are made.

1.
The values of the boosting capacitors C 1 and C 2 are large enough so as to keep their across voltages invariant.

2.
All diodes are regarded to be ideal. That is, forward drop voltage and ON-state resistance are neglected.

3.
The magnetizing inductance of the coupled inductor is much more than leakage inductance so that influence of the leakage inductance can be ignored.

4.
The turns ratios of the coupled inductors, N 1s /N 1p and N 2s /N 2p , are defined as n 1 and n 2 , respectively. 5.
The DHSIC is at CCM operation.
The driving pattern relating to the four switches is the same as that discussed in the previous section. The S 1 and S 2 are closed for D 1 T and S 3 and S 4 for D 2 T. In addition, the duty ratio of D 1 is greater than D 2 . Based on the assumptions made at the beginning of this section, states 2, 4 and 6 in Figure 4 will dominate the converter operation.

Voltage Conversion Ratio
The proposed DHSIC can be regarded as a combination of two step-up converters which are symmetrical to common ground at the input side and in series connection at the output port. Furthermore, the two step-up converters are capable of operating individually. Therefore, the obtaining of voltage conversion ratio of the DHSIC can simply be derived from a single input situation and then to augment to dual-input situation. Suppose that only the V in1 powers the DIC and both switches S 1 and S 2 are closed for D 1 T and open for (1 − D 1 )T over one switching period. The equivalents of switch ON and OFF are depicted in Figure 7. Applying voltage second balance criterion to L m1 can yield From Figure 7b, the V Lm1,on and V Lm1,off can be obtained as follows: and Substituting Equations (2) and (3) into Equation (1) can find the expression of V C1 : From Figure 7a, the voltage across capacitor C 3 , V C3 , is found by the multiplication of turns ratio n 1 and V Lm1,on , and then, from Equations (2) and (4) the V C3 can be written as According to Figure 7b, the following relationship holds: Based on Equations (3)-(6), the output voltage of the converter at SIO can be given by 1 1 2 D − According to Figure 7b, the following relationship holds: Based on Equations (3)-(6), the output voltage of the converter at SIO can be given by According to Equation (7), the switch duty ratio has to be less than 0.5, which is the converter limitation. Figure 8 depicts the relationship of voltage gain and duty ratio under different turns ratio.  According to Equation (7), the switch duty ratio has to be less than 0.5, which is the converter limitation. Figure 8 depicts the relationship of voltage gain and duty ratio under different turns ratio.
respectively. Being similar to Equation (6), the following relationship will hold under a dual-input situation.
Thus, the corresponding output voltage at DIO of the converter can be described as With respect to the DIO situation, the DHSIC has the same control scheme shown in Figure 3. The  (4) and (5) can be applied to the finding for the voltages of C 2 and C 4 . That is, V C2 and V C4 are calculated by and respectively. Being similar to Equation (6), the following relationship will hold under a dual-input situation.
Thus, the corresponding output voltage at DIO of the converter can be described as Assume that V in2 = 2V in1 , D 1 = D 2 = D, and n 1 = n 2 = n, according to Equation (11), Figure 9 represents the relationship of voltage gain versus turns ratio, while under DIO situation.
respectively. Being similar to Equation (6), the following relationship will hold under a dual-input situation.
Thus, the corresponding output voltage at DIO of the converter can be described as Assume that Vin2 = 2Vin1, D1 = D2 = D, and n1 = n2 = n, according to Equation (11), Figure 9 represents the relationship of voltage gain versus turns ratio, while under DIO situation.

Duty Cycle
Voltage Gain . Figure 9. The voltage gain versus duty ratio under the DIO situation.

Voltage Stress of Semiconductor Device
According to the structure of the DHSIC, the semiconductor devices, S 1 , S 2 , D 1, and D 2 , will have the same voltage stress. In addition, the power stage has inherently symmetrical configuration and is able to operate independently and individually at primary side. Therefore, the voltage stress of S 1 , S 2 , D 1, and D 2 can be determined from Figure 7, accordingly all of which will be equal to V C1 . From Equation (4), this voltage stress is expressed as Similarly, voltage stress of S 3 , S 4 , D 3, and D 4 can be determined by With attention to the semiconductor devices at the output port (the secondary side of the DHSIC), an associated determination is discussed in the following. While all active switches are in OFF-state, the blocking voltages of diodes D 5 and D 6 are obtained by and respectively. The V C1 and V C3 can be founded by Equations (4) and (5) in turn, and V C2 and V C4 by Equations (8) and (9). As a result, the above Equations (14) and (15) can be rewritten as respectively. Voltage stress of the output diode D O is estimated at the state that all active switches are closed and thus it will be Based on Equations (4), (5), (8) and (9), the expression of Equation (18) is rewritten as

Magnetizing Inductance Design
The minimum currents of active switches S 1 and S 2 , i Lm1,min and i Lm2,min , can be expressed as and respectively. The ∆i Lm1 and ∆i Lm2 stand for the current change on L m1 and L m2 in turn, while I Lm1 and I Lm2 are the average currents of L m1 and L m2 . Assume that the converter is lossless. Then, The I Lm1 and I Lm2 can be determined as follows: and in which the I o denotes output current. In addition, ∆i Lm1 and ∆i Lm2 can be calculated by and At the boundary, ∆i Lm1 and ∆i Lm2 are equal to zero, that is, and From Equations (26) and (27), the minimum magnetizing inductances for CCM operation have to meet the following inequality: and Suppose that the turns ratio n 1 = n 2 = n, V in2 = 2V in1 = 24 V, switching frequency f s = 40 kHz, and both switches have the same duty ratio denoted as D. In addition, the converter operates at boundary condition mode (BCM) at 25 W. Figure 10 illustrates the relationship between magnetizing inductance and duty ratio for L m1 and L m2 . condition mode (BCM) at 25 W. Figure 10 illustrates the relationship between magnetizing inductance and duty ratio for Lm1 and Lm2. The comparison with other similar converters is summarized in Table 1. It can be found that even though the DHSIC needs more power components, it achieves excellent voltage gain over other DICs in addition to that the features of galvanic isolation, continuous input current and switch voltage clamping still can be possessed.

Experimental Results
To verify the proposed DIC, a 200-W prototype is built, simulated and measured. Converter parameters and components adopted are summarized in Table 2. The control block diagram of the prototype is depicted in Figure 11. Power of input port 1 is calculated according to the detected input voltage and current, that is, Vin1,fb, and Iin1,fb, and then it is compared to a reference Pref1. The control signals for S1 and S2 are determined by the PI power controller and the carrier. Accordingly, the input power at port 1 can be readily controlled. With respect to the other part of the control block diagram, the output voltage is regulated by controlling the switches S3 and S4. With such voltage regulation, the input port 2 can accommodate the supplement to output power and thus power dispatch at both input ports is accomplished. The proposed converter adopts MCU dsPIC30F4011 to serve as system controller. Figure 12 shows the control signals and the corresponding input currents at full load under DIO situation. In Figure 12 the duty ratios of S1 and S2 are 0.32 and 0.23, respectively, which is consistent with Equation (11) for a 400-V output. Meanwhile, the switch voltages, vds1 and vds2, are measured and shown in Figure 13, from which it can be observed that there is no voltage spike on active switches. That is, the boosting capacitors C1 and C2 are able to recycle leakage energy and can effectively clamp switch voltage. Additionally, withstood voltages on the switches at port 1 and port The comparison with other similar converters is summarized in Table 1. It can be found that even though the DHSIC needs more power components, it achieves excellent voltage gain over other DICs in addition to that the features of galvanic isolation, continuous input current and switch voltage clamping still can be possessed.

Experimental Results
To verify the proposed DIC, a 200-W prototype is built, simulated and measured. Converter parameters and components adopted are summarized in Table 2. The control block diagram of the prototype is depicted in Figure 11. Power of input port 1 is calculated according to the detected input voltage and current, that is, V in1,fb, and I in1,fb , and then it is compared to a reference P ref1 . The control signals for S 1 and S 2 are determined by the PI power controller and the carrier. Accordingly, the input power at port 1 can be readily controlled. With respect to the other part of the control block diagram, the output voltage is regulated by controlling the switches S 3 and S 4 . With such voltage regulation, the input port 2 can accommodate the supplement to output power and thus power dispatch at both input ports is accomplished. The proposed converter adopts MCU dsPIC30F4011 to serve as system controller. Figure 12 shows the control signals and the corresponding input currents at full load under DIO situation. In Figure 12 the duty ratios of S 1 and S 2 are 0.32 and 0.23, respectively, which is consistent with Equation (11) for a 400-V output. Meanwhile, the switch voltages, v ds1 and v ds2 , are measured and shown in Figure 13, from which it can be observed that there is no voltage spike on active switches. That is, the boosting capacitors C 1 and C 2 are able to recycle leakage energy and can effectively clamp switch voltage. Additionally, withstood voltages on the switches at port 1 and port 2 are 34 V and 45 V, respectively, which verifies the theoretical analysis results of Equations (12) and (13). Figure 14 is the measurement of the voltages of boosting capacitors. This figure reveals that voltages of C 1 and C 2 are in turn 34 V and 45 V, both voltage magnitudes of which meet the theoretical results of Equations (4) and (8). While step change takes place from half load to full load and then drops back, Figure 15 shows the related output voltage and current. Figure 15 illustrates that constant 400-V output still can be kept with even under step change. The overshoots at step-up and step-down transitions are only 1 V and 0.7 V, respectively. With respect to SIO situation, once power failure occurs at input 1, Figure 16 shows the measured control signal, output voltage, and input current. Similarly, if at input 2, Figure 17 is the related measurement. Both figures demonstrate the operation ability of the converter at SIO situation. The measured waveform of output current is presented in Figure 18, from which it can be observed that the output current of the converter is near to be ripple-free. The efficiency of the proposed converter is measured and then shown in Figure 19, in which the peak value is about 91.4%. In the experiment, a very low level of voltage, V in1 = 12 V, is considered, therefore, which yields that higher current has to be demanded at a specific power, resulting in large conduction loss. This is the major reason why the converter efficiency is not as high as satisfied in the measurement. However, if input voltage is raised, the converter efficiency will be advanced. At single-input situation, if only the 24 V of V in2 suppled the DHSIC, measured converter efficiency is shown in Figure 20. This figure reveals that a higher voltage input can yield a better efficiency even under the operation of single input. A photo of the built-up DHSIC is shown in Figure 21.        (control signals: 10 V/div, vC1 and vC 2: 50 V/div, time: 10 μs/div)      (vgs3: 10 V/div, Vo: 500 V/div, iin2: 10 A/div, time: 10 μs/div) Figure 17. The measured waveforms of the control signal, output voltage, and input current while input 1 encounters power failure.

Conclusions
In this paper, a dual-input converter is proposed, which possesses the characteristics of ultrahigh voltage gain, continuous input currents, galvanic isolation, inherent voltage-clamp feature, and recycling the energy stored in leakage inductance. This converter is capable of controlling the dual inputs independently and individually. Moreover, it still can accomplish all the mentioned features even under the case that either input encounters power failure. That is, the converter has operation flexibility to operate at dual-input situation or single-input situation for accommodating input conditions. A maximum of measured efficient is about 91.4% at dual-input operation.