Comprehensive Analysis of a High-Power Density Phase-Shift Full Bridge Converter Highlighting the E ﬀ ects of the Parasitic Capacitances

: A phase-shift full bridge converter is analyzed in detail in continuous conduction mode for one switching cycle for both the leading and lagging legs of the primary bridge. The objective of the study is to determine how the stray capacitance of the transformer, and the capacitances of the diodes in the bridge rectiﬁer a ﬀ ect the converter functionality. Starting from some experimental results, Laplace equivalent circuit models and describing equations are derived for each signiﬁcant time interval during the switching cycle and are validated through simulations and experimental measurements. The resulting equations are of great interest in the high-power density domain because they can be used to design a clamping circuit for the output rectiﬁer bridge accurately.


Introduction
The phase-shift full bridge converter (PSFB) uses parasitic circuits elements, such as capacitances of the semiconductor devices and leakage inductances of the power transformer to provide zero voltage switching (ZVS) without any other active components. During the dead time between switching the transistors of the same leg, the converter can achieve zero voltage ZVS using the energies stored in magnetic components (mainly the power transformer leakage and magnetizing inductance) and the output capacitances of the primary bridge switches. Dead time is usually calculated using a set of predefined conditions, which results in the loss of zero voltage switching condition (ZVS) at light loads [1]. Since the zero voltage switching determines the efficiency of the converter and considering that it depends on the dead time, the relationship between the available energies, the values of the magnetic components and the parasitic capacitances of the semiconductor devices can be determined by analyzing the equivalent circuit models during switching. The values of the magnetic components, the snubbers and the capacitances of the semiconductor devices can be chosen based on this analysis.
When a PSFB is designed for high output voltage, the effect of the stray capacitance of the power transformer together with the parasitic capacitance of the secondary rectifier bridge has a significant effect on its operation [2]. This type of converters are intensely used in many of industrial areas [3], for example: Battery chargers for plug-in-electric vehicles [4][5][6], photovoltaic (PV) power systems (charging batteries or boosting the PV voltage to higher levels) [4], fuel-cell stacks, wind turbines, DC microgrid applications, lighting, etc.
The PSFB topology is represented in Figure 1. As it can be seen, the converter has three modules: The full bridge inverter, the high frequency transformer, and the output rectifier and filter. The converter efficiency [8].  In most cases, high insulation requirements are needed between the primary and the secondary windings of the power transformer to satisfy the safety standards for this converter. This leads to large leakage inductance in primary and secondary sides. A large number of secondary turns required for high step-up and high voltage applications leads to an increased capacitance between the windings of the transformer, significantly deteriorating the performance of the converter [3,9]. The parallel capacitance of the secondary rectifier diodes adds to the stray capacitance of the transformer further increasing its effects. Another drawback of the converter is the dependency of the ZVS on the load conditions. The loss of ZVS causes not only a decrease in efficiency, but also results in high electromagnetic interference at light load. There are methods to increase the ZVS range by adapting the dead-time based on load condition [10,11]. Moreover, new control methods where used to increase the ZVS at light loads [12][13][14][15]. Modification of the power topology was proposed to extend the ZVS range in References [16][17][18][19]. By properly analyzing the switching behavior of the converter, the ZVS range can be extended without altering the control or the topology of the converter to some extent.
Many studies concentrate on the parasitic elements and how can they degrade the efficiency of the converter. None of these papers considers the stray capacitance of the transformer or the capacitance of the output rectifier. The parasitic elements of the high voltage transformer are analyzed in different papers, but only in predetermined conditions: For example, in Reference [3] only in discontinuous conduction mode (DCM) and for a PSFB converter with pure capacitive filter; in Reference [9] the effect of the transformer capacitance only on the leading leg from current drop perspective; in References [20,21] a discussion on voltage oscillations across secondary diodes in a PSFB converter, but not analyzing in every detail a complete switching interval.
The design of high voltage PSFB converter has many degrees of freedom which complicates the selection of the components [22]. Finding an optimized solution (highest power density, efficiency or lower cost) requires comprehensive analytical models and equations that account for the most harmful parasitic elements. This work concentrates on a detailed analysis of the PSFB converter that accounts parasitic influences, namely: Stray capacitance of the transformer secondary winding and the capacitances of the diodes in the bridge rectifier. The analysis is performed in continuous conduction mode for both the leading and lagging leg of the primary bridge for a complete switching cycle.

Motivation
Most articles nowadays start from method explanation and simulations followed by experimental results for validation. In this paper, a different approach is proposed. As presented in Figure 2, Energies 2020, 13, 1439 3 of 20 one can see the differences between a simulation-based analysis and the waveforms obtained during experimental measurement. Starting from these differences, a mathematical analysis using Laplace equivalent models, together with Spice simulations for the different working time intervals are proposed for better understanding the influence of the parasitic capacitance on the phase shift converter [23]. The Laplace equivalent models emphasize the effects of the parasitic capacitance and provide the designer with an in-depth understanding of how to compensate them in order to provide a better design. The simulations were carried out to validate the theoretical analysis and provide a faster and more intuitive tool for the designers. A complete switching cycle of the converter was considered for the analysis. For an in-depth analysis, this cycle was divided into seven time intervals to better highlight the effect of the parasitic capacitance. For each time interval, Laplace equivalent models are provided in the paper followed by a simulation specific built for each situation. In the simulations, the component values used are the same as for the built experimental model. The results obtained through simulations are compared with the ones obtained during experiments. Comparing the numerical values, it can be seen that the mathematically equivalent model and simulations are validated. In some cases, the small inaccuracies that appear are due to other parasitic elements that were not taken into account intentionally to have a simple equivalent model that can be used with ease. As presented in the paper, the equations obtained can be used for instance as a basis for the design of an active snubber circuit that will increase the efficiency and ease the thermal enclosure design. Choosing the correct components through a minimum number of steps is every designer's goal.

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The experimental model from which the analysis started was used to provide data to check the 107 accuracy of the Laplace equivalent models and simulations.

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The phase shift converter was designed for the following specifications: The input voltage of The experimental model from which the analysis started was used to provide data to check the accuracy of the Laplace equivalent models and simulations.
The phase shift converter was designed for the following specifications: The input voltage of the converter reflected in the secondary is V in = 250 V, and the output voltage is V out = 173 V. The primary leakage inductance is L r_p = 5 µH, the transformer ratio is n = 0.6, and the output inductor is L out = 280 µH.
The secondary peak voltage and the oscillations caused by L r = 14 µH inductance (the sum of the leakage inductances referred to the secondary that will be explained later) and C s capacitance-total stray capacitance of the transformer and rectifier capacitances (will be demonstrated later) are presented in Figure 3.
Where Io = 2.3 A is the output current. Equation 2 will be later demonstrated in the article.

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The Cr capacitor is fully charged in about 97 ns as can be observed in Figure    138 As it can be seen from secondary rectified voltage, the frequency of oscillations is f r = 4.167 MHz. Thus, C s capacitance can be estimated as: where L r =14 µH. Also, the discharge time interval of C r (the switches equivalent output capacitance equal to 767 pF) can be estimated as: where I o = 2.3 A is the output current. Equation (2) will be later demonstrated in the article. The C r capacitor is fully charged in about 97 ns as can be observed in Figure 4: Where Io = 2.3 A is the output current. Equation 2 will be later demonstrated in the article.

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The Cr capacitor is fully charged in about 97 ns as can be observed in Figure    Although simulation tools can always be used for simulating the switching converters in a much easier way, the circuit parameters remain in non-closed form, and it is difficult to tell the impact of a certain design parameter on the results. Moreover, experiments often take time, and additional delay will be expected if changes in magnetic components are needed. On the other hand, a mathematical model can give very intuitive information, which can always help the designer to (1) fully understand the operation of the switching states; (2) reduce the number of iterations for optimization in experiments; (3) find worst case/corner case for testing; (4) analyze component tolerance impacts, etc.

The Model of the Converter
In Figure 5a, an equivalent electric circuit of a high frequency transformer is presented, with all the elements referred to the secondary side. R' w1 and R w2 are the resistances and L' lkp , and L lks are the leakage inductances of the primary and secondary windings, L m is the magnetizing inductance of the secondary, C' 1 and C 2 are the self-capacitances of the primary and secondary windings, C 12 the mutual capacitance between the windings and V' 1 , V 2 are the voltages of the primary and secondary sides. For the analyzed converter, the primary and the secondary inductances of the transformer are small compared to the magnetizing inductance. The voltage drop across these inductances is small; thus, the stray parasitic capacitances can be modeled by a single capacitor, connected as in Figure 5b equal to: C sec ≈ C' 1 + C 2 with C 12 neglected.      If the effects of the winding resistances and of the magnetizing inductance are neglected, then a simplified transformer model is obtained, Figure 5c, where L r is the sum of the leakage inductances.
Due to design considerations, the transformer ratio is equal to 0.6, resulting in the equivalent circuit of the PSFB converter, Figure 6, where G 1 , G 2 , G 3 and G 4 are the gate drive signals, V cs is the voltage on the stray capacitance, I r is the current through the L r inductance, and V rec is the secondary rectified voltage. The rectifier capacitances are also included in the total stray capacitance of the transformer C s = C sec + C DIODES . When I o flows through D 1 , D 4 C DIODES = C D2 + C D3 and vice-versa when D 2 and D 3 conduct.

154
Due to design considerations, the transformer ratio is equal to 0.6, resulting in the equivalent 155 circuit of the PSFB converter, Figure 6, where G1, G2, G3 and G4 are the gate drive signals, Vcs is the 156 voltage on the stray capacitance, Ir is the current through the Lr inductance, and Vrec is the secondary and D3 conduct.   Whenever possible, the parasitic elements (leakage inductances of the transformer associated with semiconductor parasitic capacitances) can be used in an advantageous way to facilitate the resonant transition and to achieve ZVS. In Figure 1 the resonant inductor is depicted by L r_p that can be an external inductor added to the schematic but in this case, the leakage inductances of the transformer will be used as the resonant inductor, L r , to achieve ZVS: L r = L lkp + L lks . C' o1 , C' o2 , C' o3 , C' o4 are the output capacitances of the switches and I r and V inv are values referred to the secondary. Figure 7 illustrates the operation waveforms of the converter.

Converter Operation
During t1-t2, if there is enough energy stored in Lr, C'o2 capacitor is completely discharged, and 180 C'o1 is charged to Vin. Thus, at t2, the body diode of Q2 turns ON, allowing ZVS turn ON for Q2.

181
Considering Cr = C'o1 + C'o2 the equivalent output capacitance of Q1 and Q2 transistors and neglecting 182 the secondary parasitic capacitance Cs, the Laplace equivalent circuit corresponding to this time 183 interval is presented in Figure 8.

Operation during [t 1 -t 3 ]
In the first analysis, the influence of the capacitance C s is neglected. Before t 1 , transistors Q 1 and Q 3 together with diode D 1 and D 4 are ON. In the same time, the output capacitor C' o2 of the Q 2 transistor starts discharging. The output current I o flows through D 1 , D 4 , D 3 and D 2 , so that the following relationships can be written.
During t 1 -t 2 , if there is enough energy stored in L r , C' o2 capacitor is completely discharged, and C' o1 is charged to V in . Thus, at t 2 , the body diode of Q 2 turns ON, allowing ZVS turn ON for Q 2 . Considering C r = C' o1 + C' o2 the equivalent output capacitance of Q 1 and Q 2 transistors and Energies 2020, 13, 1439 7 of 20 neglecting the secondary parasitic capacitance C s , the Laplace equivalent circuit corresponding to this time interval is presented in Figure 8.

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The equation describing the circuit in Figure 8 is: If the angular frequency is 1 r rr LC   then the current through Cr is: Applying the Laplace inverse transform to (5) and shifting to t1, results that Cr is discharged 190 with the current: The Cr capacitor voltage is: From (7) results that the completely discharge time interval of Cr can be estimated as: For the values used in the simulation presented in Figure 9: The equation describing the circuit in Figure 8 is: If the angular frequency is ω r = 1 √ L r C r then the current through C r is: Applying the Laplace inverse transform to (5) and shifting to t 1 , results that C r is discharged with the current: The C r capacitor voltage is: From (7) results that the completely discharge time interval of C r can be estimated as: For the values used in the simulation presented in Figure 9: L r = 14 µH, V in = 250 V, I o = 2.3 A, using (8) ∆t will be 97 ns. The same result for the time needed to discharge C r is obtained in simulation, Figure 10. At t 1 all the diodes (D 1 , D 2 , D 3 , D 4 ) will start to conduct immediately.

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The equation describing the circuit in Figure 8 is: If the angular frequency is 1 r rr LC   then the current through Cr is: Applying the Laplace inverse transform to (5) and shifting to t1, results that Cr is discharged 190 with the current: The Cr capacitor voltage is: From (7) results that the completely discharge time interval of Cr can be estimated as: For the values used in the simulation presented in Figure 9: Lr = 14 µ H, Vin = 250 V, IO = 2.3 A, Figure 9. Spice equivalent schematic for the discharge of Cr. If one considers the influence of the Cs secondary parasitic capacitance, which is assumed to be 202 charged at t1, the Laplace equivalent schematic of the converter is presented in Figure 11. It will be 203 later demonstrated that Cs is charged (for the worst case) at: For example, if Lr = 14 µ H and Lout = 280 µ H, then VCs(0) = 16.4 V.

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The equations describing the circuit from Figure 11 In (11) and (12)

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Applying the Laplace inverse transform to (12) and shifting to t1 results: If one considers the influence of the C s secondary parasitic capacitance, which is assumed to be charged at t 1 , the Laplace equivalent schematic of the converter is presented in Figure 11. It will be later demonstrated that C s is charged (for the worst case) at: For example, if L r = 14 µH and L out = 280 µH, then V Cs (0) = 16.4 V.
The equations describing the circuit from Figure 11 are: After simple mathematical manipulations (10) becomes: From (11), results that the expression of the current through the C s capacitor is: In (11) and (12), C 1 = C r C s C r +C s and ω 1 = 1 Applying the Laplace inverse transform to (12) and shifting to t 1 results:

201
If one considers the influence of the Cs secondary parasitic capacitance, which is assumed to be 202 charged at t1, the Laplace equivalent schematic of the converter is presented in Figure 11. It will be 203 later demonstrated that Cs is charged (for the worst case) at:

205
The equations describing the circuit from Figure 11 In (11) and (12) Figure 11. Laplace equivalent circuit corresponding to the discharge of Cr and Cs. From (13) the voltage across the C s capacitor can be calculated as: Solving the equation v cs (t) = 0 V one gets: ∆t = 30 ns. The current through the resonant inductor is: The capacitor C r will be discharged according to: After ∆t = 30 ns the voltage on C r will be: V cap = 157 V and I rt = 2.16 A. The Spice circuit is represented in Figure 12, and the simulation results are shown in Figure 13.

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The current through the resonant inductor is: The capacitor Cr will be discharged according to: After Δt = 30 ns the voltage on Cr will be: Vcap = 157 V and Irtʹ = 2.16 A.

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The Spice circuit is represented in Figure 12, and the simulation results are shown in Figure 13.

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As can be seen in Figure 13 the diodes will turn ON immediately after Vcs reaches zero, starting 225 from its initial value before Q1 turns OFF. At this moment t' = 30 ns the voltage on the Cr capacitor Solving the equation vcs(t)=0 V one gets: Δt =30 ns.

215
The current through the resonant inductor is: The capacitor Cr will be discharged according to: After Δt = 30 ns the voltage on Cr will be: Vcap = 157 V and Irtʹ = 2.16 A.

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The Spice circuit is represented in Figure 12, and the simulation results are shown in Figure 13.  As can be seen in Figure 13 the diodes will turn ON immediately after Vcs reaches zero, starting 225 from its initial value before Q1 turns OFF. At this moment t' = 30 ns the voltage on the Cr capacitor As can be seen in Figure 13 the diodes will turn ON immediately after V cs reaches zero, starting from its initial value before Q 1 turns OFF. At this moment t' = 30 ns the voltage on the C r capacitor that is also discharging reaches the value of 157 V and the current through the L r inductor is 2.16 A. The C r capacitor needs in this case 97 ns to completely discharge from its initial value.
In Figure 14, a detailed set of waveforms is presented for the time interval corresponding to [t 1 -t 2 ]. It can be observed that the values obtained with the mathematical and simulation model match closely the experimental measurements. V cr is the voltage measured on the primary of the transformer and corresponds to V inv from Figure 6, V cs is the voltage on the secondary, V rec is the rectified secondary voltage, and I Lr is the output current in this case. that is also discharging reaches the value of 157 V and the current through the Lr inductor is 2.16 A.

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The Cr capacitor needs in this case 97 ns to completely discharge from its initial value.

228
In Figure 14

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At tʹ when Cs is discharged, the Laplace equivalent circuit presented in Figure 15 can be used to 237 compute the Cr voltage.
where Vdiff is the difference between the input voltage and the initial voltage of Cr at tʹ and Irtʹ is the At t' when C s is discharged, the Laplace equivalent circuit presented in Figure 15 can be used to compute the C r voltage. V where V diff is the difference between the input voltage and the initial voltage of C r at t and I rt is the current through L r at t . that is also discharging reaches the value of 157 V and the current through the Lr inductor is 2.16 A.

227
The Cr capacitor needs in this case 97 ns to completely discharge from its initial value.

228
In Figure 14

236
At tʹ when Cs is discharged, the Laplace equivalent circuit presented in Figure 15 can be used to 237 compute the Cr voltage.
where Vdiff is the difference between the input voltage and the initial voltage of Cr at tʹ and Irtʹ is the  The diodes D 2 , D 3 will start to conduct after t when C s is completely discharged. At t" = 97 ns when V cr (t") = 0 the resonant inductor current, I r , is flowing through the body diode D in2 of Q 2 , decreasing with a slope equal to V in /L r . Now Q 2 can be switched ON. The current through D 1 is decreasing and through D 3 is increasing. At t 3, D 1 current is zero and I r = I o .
When C s is charged at a low voltage, its influence on the C r discharging time is negligible.

Operation during [t 3 -t 4 ], immediately after t 3
At t 3 , D 1 and D 4 diodes turn OFF, and the output current continues to flow through D 3 and D 2 . For a short time after t 3 the current through L out can be considered constant, and this inductance is replaced by a constant current source. The Laplace equivalent model corresponding to this time interval is presented in Figure 16.

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The Laplace equivalent model corresponding to this time interval is presented in Figure 16.

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The equations describing the circuit from Figure 16 After simple mathematical manipulation of (21) the expression of the Cs current is:

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The voltage across the Cs capacitor can be calculated as: As it can be deduced from (23), Vcs voltage reaches its maximum value Vcs.max = 2Vin after a time 261 interval equal to T/2 = π/ω. This equation is very useful for designing the output clamping circuit.

262
Spice simulation for the schematic in Figure 17 describing the converter immediately after t3 is 263 presented in Figure 18. The equations describing the circuit from Figure 16 are: After simple mathematical manipulation of (21) the expression of the C s current is: where ω = 1 √ L r C s . The voltage across the C s capacitor can be calculated as: As it can be deduced from (23), V cs voltage reaches its maximum value V cs.max = 2V in after a time interval equal to T/2 = π/ω. This equation is very useful for designing the output clamping circuit.
Spice simulation for the schematic in Figure 17 describing the converter immediately after t 3 is presented in Figure 18.

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In Figure 19 are highlighted the experimental results for the interval t3-t4 immediately after t3. It

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In Figure 19 are highlighted the experimental results for the interval t3-t4 immediately after t3. It   As it can be observed in Figure 18, immediately after t 3 the maximum voltage on the C s capacitor reaches the double input value, in this case, V in = 250 V. The value represents the voltage measured on the secondary side of the transformer.
In Figure 19 are highlighted the experimental results for the interval t 3 -t 4 immediately after t 3 . It can be observed that there is a difference between the simplified model used in the simulation and the experimental values. This difference is due to the fact that the simulation takes into account the worst-case scenario for the maximum possible V cs voltage (obtained for worst-case R 1 = 0 Ω).
For the experimental setup, if a secondary parasitic equivalent resistance R 1 = 70 Ω is considered, the damping ratio of the secondary voltage is given by: From (24) results that secondary peak voltage can be estimated with:

298
The equations describing the circuit in Figure 21 Figure 19. Measurement results immediately after t 3.

Operation during [t 4 -t 5 ]
At t 4 , Q 3 turns off, and the energy transfer from primary to the output stops. The output capacitor C' o3 of Q 3 starts to charge, and the output capacitor of Q 4 starts to discharge. If one considers C r = C' o3 + C' o4 , then the equivalent schematic of the converter corresponding to this time interval is presented in Figure 20.
Since only D 1 and D 4 are on, results that C r starts to be charged with an approximatively constant current (the output current I o ), thus in general, this time interval is very narrow.
In this case, the voltage across the C r capacitor is given by:  interval is presented in Figure 20.

287
Since only D1 and D4 are on, results that Cr starts to be charged with an approximatively 288 constant current (the output current Io), thus in general, this time interval is very narrow.

289
In this case, the voltage across the Cr capacitor is given by:  From Equation (26), results that the charging time interval of the C r capacitor can be estimated with (27) supposing that during this time interval the capacitor C s will remain charged at the approximately same voltage V in . A detailed analysis which takes into account the influence of C s can be made, as in Section 4.1.
The equations describing the circuit in Figure 21 are:

303
The equivalent circuit corresponding to this time interval is presented in Figure 22, supposing 304 that Cr is already charged. During [t4ʹ-t5] time interval, as seen in Figure 23, the energy stored in Cs 305 shall be evacuated through D1 and D4.

306
From (23) results that Cs current is given by: Applying the Laplace inverse transform to (29) and shifting to t4ʹ, results that Cs is discharged by a sinusoidal current, as in (22). The equation of the voltage across the Cs capacitor becomes in this 309 case: As supposed before, the Cr capacitor will start to charge according to Equation    The equivalent circuit corresponding to this time interval is presented in Figure 22, supposing that C r is already charged. During [t 4 -t 5 ] time interval, as seen in Figure 23, the energy stored in C s shall be evacuated through D 1 and D 4 .
From (23) results that C s current is given by: Applying the Laplace inverse transform to (29) and shifting to t 4 , results that C s is discharged by a sinusoidal current, as in (22). The equation of the voltage across the C s capacitor becomes in this case: As supposed before, the C r capacitor will start to charge according to Equation (26), while for the first part of this period of time the voltage on the C s capacitor remains constant at the 250 V in this case. The energy stored in C s shall be evacuated through the D 1 and D 4 diodes.

303
The equivalent circuit corresponding to this time interval is presented in Figure 22, supposing 304 that Cr is already charged. During [t4ʹ-t5] time interval, as seen in Figure 23, the energy stored in Cs 305 shall be evacuated through D1 and D4.

306
From (23) results that Cs current is given by: Applying the Laplace inverse transform to (29) and shifting to t4ʹ, results that Cs is discharged by 308 a sinusoidal current, as in (22). The equation of the voltage across the Cs capacitor becomes in this 309 case: As supposed before, the Cr capacitor will start to charge according to Equation

316
In Figure 24 are highlighted the experimental results for the interval t4-t5. It can be observed that 317 the results match closely the values obtained with the mathematical and simulation models. In Figure 24 are highlighted the experimental results for the interval t 4 -t 5 . It can be observed that the results match closely the values obtained with the mathematical and simulation models.

Operation during [t 5 -t 7 ]
From (30) results that at t 5 (after a time interval equal to T/4 = π/2ω), the voltage across C s reaches zero, and the I cs current reaches its maximum value. After this time interval, due to the reverse voltage polarity on C s , the energy stored in it shall be evacuated almost instantaneous through D 2 and D 3 , which turn ON and keep the voltage on C s equal to zero. At t 6 , Q 4 turns ON with ZVS, and the primary output reflected current continues to flow through the body diode D in4 of Q 4 . The D 1 and D 4 diodes are turned ON together with D 3 and D 2 until t 7 , when the L r current reaches again the value of the output current reflected in the primary of the transformer. After t 7 , the output current flows again only through D 1 and D 4 . If one considers that in [t 5 -t 7 ] time interval the L r current is approximatively constant and the diode currents i D1 = i D4 and i D3 = i D2 , then the equivalent schematic of the converter corresponding to this time interval is presented in Figure 25.
The equations describing the circuit in Figure 25 are: From (31) results that:  Since this difference between the output current and the reflected primary current is given by the current drop through C s at t 5 , results that: where I D1 and I D2 are the current values through D 1 and D 2 in t 5 and I cs.max is the maximum value of the C s current. The diodes D 2 and D 3 are turning OFF at t 7 , when the current through L r reaches the value of the current through L out .
The equations describing the relation between the L r and L out currents are: Since the L r and L out currents are again equal at t 7 , results that: From (35) results that [t 5 -t 7 ] time interval can be estimated as: 1.2 µs.

Operation during [t 7 -t 8 ]
At t 7 , D 2 and D 3 diodes turn OFF, and D 1 and D 4 continue to stay ON until t 8 , when Q 2 transistor turns OFF. The equivalent circuit from Figure 26 presents the Laplace model of the converter corresponding to [t 7 -t 8 ] time interval. In this case, the initial currents through L r and L out have no influence.
If Z p = sL r /sC s sL r +1/sC s = sL r 1+s 2 L r C s is the impedance of the parallel connection L r -C s and ω 2 = 1 L out Lr L out +Lr C s then (37) becomes: Applying the Laplace inverse transform to (38), results that the voltage across the C s capacitor in [t 7 -t 8 ] is: Spice simulation for the schematic in Figure 27 describing the converter in [t 7 -t 8 ] interval is presented in Figure 28. As can be observed the C s capacitor charges at the voltage deduced with Equation (9). So this is the worst-case values of V cs (0) for this specific analysis.
Spice simulation for the schematic in Figure 27 describing the converter in [t7-t8] interval is 363 presented in Figure 28. As can be observed the Cs capacitor charges at the voltage deduced with 364 Equation (9). So this is the worst-case values of Vcs(0) for this specific analysis.
Spice simulation for the schematic in Figure 27 describing the converter in [t7-t8] interval is 363 presented in Figure 28. As can be observed the Cs capacitor charges at the voltage deduced with 364 Equation (9). So this is the worst-case values of Vcs(0) for this specific analysis. As it can be deduced from (39), v cs voltage reaches the maximum value V cs.max = 16.4 V after a time interval equal to T 2 /2 = π/ω 2 : V cs.max = 2 V out L r L out + L r (40) In Figure 29 can be observed that the voltage across the C s capacitor in [t 7 -t 8 ] is V cs = 16.4 V corresponding with the value obtained with Equation (40).

Conclusions
This paper presents a detailed analysis of the PSFB converter that accounts for the stray capacitance of the transformer secondary winding and the capacitances of the diodes in the bridge rectifier. The analysis was performed in continuous conduction mode for both, leading and legging leg of the primary bridge and for a complete switching cycle, starting from an equivalent electric circuit of a high frequency transformer, with all the elements referred to the secondary side. The complete switching cycle considered for the analysis was divided into seven time intervals to better highlight the effect of the parasitic capacitance. A simplified Laplace equivalent circuit for each operation time interval was developed and the corresponding equations where derived. The values obtained through mathematical manipulation are compared with the ones obtained with the Spice simulation models created for each time interval. The simulation models validate the mathematical description on each time interval and provide an intuitive and easy to adapt the method for analyzing a phase shift converter in detail. Equations (9) and (23) can be used to design active snubbers. The effect of the stray capacitance can be observed in the experimental waveforms presented in Figure 29. Because of the short amount of time and small value that the V cs (0) exhibits most of the time, its presence is ignored by designers resulting in flawed designs. The experimental waveforms were measured on the PSFB converter prototype. It can be observed that the experimental measurement prove that the mathematical model and the equivalent simulation circuits are valid and can be used for design optimizations.

Discussion
The main objective of the paper is to highlight and better understand the effects of the parasitic capacitances on the PSFB. By using the equations and simulation models presented in Section 4 the design process of such a converter simplifies, and there is no need for implementing new complicated control techniques if the negative effects of the stray capacitance are taken into account. By determining the maximum voltage on the stray capacitance, an active clamping circuit can be designed. As highlighted in the Introduction section, such high power density converters are needed more and more in the automotive industry, due to the development of electric cars and off and on board charging stations. Using active snubbers in this equipment is necessary, due to high-efficiency requirements and space constraints that affect the heat dissipation needed for the passive snubbers approach. This type of analysis, presented in this paper, helps designers and scientist to better understand the effects that appear in high density power converters. If these effects are ignored it can